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The Three Vectors of Coherent Evolution

headshot of Paul Momtahan

May 27, 2021
By Paul Momtahan
Director, Solutions Marketing

In many cultures, three is a lucky, symbolic, or powerful number. It is a lucky number in China. In Christianity there is the Holy Trinity (Father, Son, and Holy Spirit). The ancient Greek philosopher Pythagoras and his followers considered it the perfect number representing harmony, wisdom and understanding. It is also the number of time – past, present, future; birth, life, death; beginning, middle, end. We even say “good things come in threes” and “third time’s a charm”. And for coherent technology evolution, three is also becoming an important number. Let me explain.

As discussed in a previous blog, the digital ASIC/DSP plays a key role in a modern coherent transceiver, in terms of the performance and functionality as well as having a large influence on the power consumption and footprint. And as the digital ASIC/DSP is made with silicon it is subject to the same CMOS process node improvement cycle, made famous by Moore’s Law, that drives the entire chip industry.

CMOS Process Node GainsFigure 1– CMOS Process Node Gains

As shown in Figure 1, each major new CMOS process node provides significant gains in terms of processing power, power consumption, and area. For example, 7 nm, which is the current state-of-the-art for coherent digital ASIC/DSPs, gives a 30% performance improvement or a 60% power reduction, and a 70% area reduction, relative to 16nm. Beyond 7 nm is 5 nm which is driving the current generation of high-end mobile phones (i.e., Apple iPhone 12). High-end mobile chips with the high volumes that can justify the billions of dollars required to build a fab with the latest process node, and with a need for high performance and low power consumption, are now the early adopters of each new major CMOS process node. Beyond 5 nm, the silicon industry has a roadmap to 3 nm in 2022, and, according to the IEEE’s International Roadmap for Devices and Systems (IRDS), 2.1 nm in 2025, 1.5 nm in 2028, 1 nm in 2031, and 0.7 nm in 2034. Though it is important to note that these nm-based generation descriptors no longer have a direct relationship with any specific geometry of the silicon, such as the gate length.


The improved performance, power consumption, and density of each generation of silicon has enabled digital ASIC/DSP designers to build more powerful chips enabling dramatic improvements in coherent performance. For example, the first generation of 100G coherent ASIC built with 65 nm CMOS had tens of millions of transistors. A second generation of 100G coherent ASIC based on 40 nm had a few hundred million transistors. 28 nm ASICs, such as the one used in Infinera’s ICE4 optical engine, typically have around 1.5 billion transistors. 16 nm ASICs, such as the one powering Infinera’s CHM2T 2 x 600 Gb/s sled for the GX G30, typically have around 2.5 billion, while the 7 nm ASIC in Infinera’s ICE6 embedded optical engine has more than 5 billion transistors. More transistors equate to more processing power and have enabled new features in each coherent generation, with major improvements in wavelength-capacity reach and spectral efficiency.

To address a diverse set of requirements and applications, coherent transceivers are now evolving in line with three vectors, as shown in Figure 2. This is enabled by the previously described CMOS process node advancements, with additional improvements in photonic technology also playing an important role.

The Three Vectors of Coherent EvolutionFigure 2 – The Three Vectors of Coherent Evolution

Vector A:  Maximize Performance and Advanced Optical Features

The first option for leveraging CMOS and photonic improvements focuses on maximizing performance in terms of headline wavelength capacity, wavelength capacity-reach, and spectral efficiency. This requires leveraging the highest possible baud rates and the most advanced optical features, with the most powerful ASICs. However, as the CMOS technology evolves it can enable high-end functionality that was previously only available with embedded optical engines, in pluggable form factors.

Vector B: Minimize Space and Power

A second option for leveraging CMOS improvements is to build a more compact and more power-efficient ASIC, reducing the Watts per Gb/s, rack units per Gb/s, and enabling compact pluggable form factors such as CFP2, OSFP, and QSFP-DD. Embedded optical engines can also reduce space and power with CMOS enhancements but this is typically a secondary objective compared to maximizing performance and implementing advanced optical features, with improvements in Watts per Gb/s per km often a byproduct of better wavelength capacity-reach.

For coherent pluggables, minimizing space and power is a much higher priority. ASIC/DSPs optimized for 400 Gb/s coherent pluggables typically have around 1.5 billion transistors compared to the more than 5 billion for the ASIC/DSP in Infinera’s ICE6. A 400 Gb/s pluggable ASIC would also be typically around 25% of the area of the ICE6 ASIC/DSP. ASICs for pluggables will also typically support modes with different levels of performance and power consumption, depending on the application and the form factor constraints. However, leveraging the same CMOS process node while being constrained by size and power, these pluggables cannot deliver the same performance and advanced features as larger, more power-hungry embedded ASICs, though they do offer compensatory benefits of pluggability, compact size, lower power, and typically lower unit costs.

Vector C:  Integrate System-Level Functions

Shelf and Card-level Features Migrate to PluggablesFigure – Shelf and /Card-level Features Migrate to Pluggables

A third option for leveraging CMOS process node improvements is the integration of system-level functionality, migrating functions that previously would have lived in the shelf, shelf controller, or interface card into the coherent transceiver. Embedded optical engines have already typically incorporated several previously card-level functions such as encryption, framing, and some multiplexing. However, this vector enables the further integration of shelf/card functions into the coherent transceiver. For example, the integration of functions such as remote management, in-band communications channel, topology awareness, optical spectrum analyzer, streaming telemetry, and VLAN awareness enables an XR optics pluggable to act as a virtual transponder, providing the option of useful demarcation between the router and the optical network.

Vector Prioritization: Pluggables and Embeddeds

As shown in Figure 4, embedded optical engines and different pluggables (examples A, B, and C in the diagram) prioritize these three vectors differently. Embedded optical engines tend to focus on the first vector, performance, and advanced optical features, with a secondary emphasis on power/space and some integration of systems-level features such as encryption and framing/multiplexing. For example, Infinera’s ICE6 embedded optical engine’s digital ASIC/DSP with 5+ billion transistors provides the processing power for advanced features such as long codeword probabilistic constellation shaping (LC-PCS), 2nd generation Nyquist subcarriers, dynamic bandwidth allocation, and SD-FEC gain sharing which, together with an ultra-high baud rate and indium phosphide photonic integration, enable it to maximize capacity-reach. The ICE6 ASIC also integrates encryption and multiplexing, while Infinera’s GX compact modular platform can deliver power consumption of less than 0.2W/Gb/s with ICE6.

Different Prioritizations of the Three VectorsFigure -Different Prioritizations of the Three Vectors

As another example of how these three vectors can be prioritized,  XR optics leverages a smaller, lower power digital ASIC/DSP (relative to ICE6) that enables compact pluggable form factors including QSFP-DD and CFP2. In addition to a point-to-point option, Nyquist subcarrier technology enables the industry’s first point-to-multipoint coherent. XR optics also integrates multiple systems-level functions, as described previously, enabling it to act as a virtual transponder. Benefits can include fewer optical transceivers, CapEx that aligns with actual bandwidth requirements, multi-generational interoperability, eliminated intermediate aggregation equipment, and maximized router efficiency, with total cost of ownership savings of up to 70%.

To learn more about this topic, download the new Infinera white paper “Pluggables, Embedded Optical Engines, and the Three Vectors of Coherent Evolution”.