Moore and Shannon: A Tale of Two Laws

A 1948 paper published by Claude Shannon, the mathematician, electrical engineer, and information theorist who then worked at Bell Labs, established what became known as Shannon’s law, otherwise known as the Shannon-Hartley theorem. This law/theorem puts  a limit on the amount of information that can be communicated over a channel with a given bandwidth and amount of noise with the equation C/B = Log₂ (1+SNR), where C is the maximum achievable channel capacity, B is the bandwidth, and SNR is the ratio of signal power to noise power.

In 1965, Gordon E. Moore, cofounder of Intel, predicted that the number of transistors in a given unit of space on a chip would double every two years. This prediction has largely held true since the 1970s – in fact, if anything, it has doubled more quickly than Moore predicted, and has become known as Moore’s law. This “law” enables dramatic increases in computer processing power alongside reductions in cost and power consumption.

In 1971, Intel’s 4004 processor, based on a 10 µm (10^-5 meters) technology comprising 2,250 transistors, was capable of 0.092 million instructions per second (MIPS). In 2020, AMD’s Ryzen Threadripper 3990X, based on a 7 nm (7×10^-9 meters) technology, has 3.8 billion transistors and is capable of 2,356,230 MIPS. In both transistors and MIPS, the improvement has been more than the millionfold that doubling every two years for 40 years (2¹⁰ = 1,048,576) would predict. More recently, Moore’s law has worked its magic on solid-state memory, with a 128 megabyte flash drive in 2003 costing approximately the same (~$30) as a 1 terabyte flash drive in 2020, meaning bytes per dollar has doubled 10 times in 17 years.

Figure 1: High-level coherent transceiver building blocks

But what do these two “laws” have to do with each other?

Quite a lot, in fact. As optical communications has shifted to coherent transmission and as coherent transmission has evolved, we are now getting tantalizingly close to the maximum achievable channel capacity described by Shannon’s law, the Shannon limit. Coherent transceivers themselves, as shown in Figure 1, consist of a digital ASIC/DSP, analog electronics (drivers, transimpedance amplifiers), and photonics (lasers, modulators, photodetectors, passive functions, etc).

The digital ASIC/DSP plays a critical role in the coherent transceiver, both on the transmit and receive side. Many of the advanced features that take us closer to the Shannon limit, including high-order modulation, Nyquist subcarriers, and probabilistic constellation shaping, are functions of the ASIC/DSP. The ASIC/DSP also has an important role to play in terms of operating with very high baud rates, and it accounts for a significant proportion of the power consumption and footprint of a modern coherent transceiver.

High baud rates and advanced features require lots of processing power in the ASIC/DSP, which in turn requires the latest silicon technology with the smallest CMOS process node. The first generation of 100G coherent was based on a 65 nm process node. This later evolved to 40 nm, which enabled enhanced capabilities such as soft-decision forward error correction. The 200G generation, with flexible modulation including 8QAM and 16QAM, was based on 28 nm process node silicon, as was a 400G generation that increased the baud rate and/or modulation to achieve up to 400 Gb/s per wavelength. 16 nm silicon enabled both a 600G generation with higher baud rates and more advanced modulation and more power-efficient 200G generation DSPs. More recently, 7 nm silicon is enabling both an 800G generation at the high end and 400 Gb/s in compact pluggable form factors.

Table 1: High-end coherent generations and CMOS process nodes

With each subsequent generation of silicon technology (CMOS process node), coherent technology has evolved to have higher data rates, more advanced features, and greater spectral and power efficiency. This is made possible by the (fabless) semiconductor ecosystem shown in Figure 2. With the exception of a small number of integrated device manufacturers such as Intel, most companies, including all communications equipment manufacturers; many fabless chip companies, including the likes of Broadcom, Nvidia, and Qualcomm; and even Apple, rely on third-party foundries to manufacture their silicon chips for them. The leading foundries are Taiwan’s TMSC with over 50% market share and South Korea’s Samsung Electronics with a little under 20%, followed by Global Foundries (U.S.), UMC (Taiwan), and SMIC (China), with the latest technology available from TMSC (7 nm, 5 nm) and Samsung (7 nm). These foundries, in turn, rely on semiconductor manufacturing equipment from other companies. The leading vendors of semiconductor manufacturing equipment include Dutch company AMSL; U.S. companies Applied Materials, KLA, LAM Research, and Teradyne; and Japan’s Tokyo Electron. The ecosystem also relies on design software from companies such as Mentor Graphics, Cadence, and Synopsys, all American. Coherent technology also leverages off-the-shelf building blocks, known as standard cells, and intellectual property from a wide range of companies, which are used to accelerate the design of complex chips.

Figure 2: The (fabless) semiconductor ecosystem

So, to conclude, the increases in processing power described by Moore’s law and brought to life by the global semiconductor ecosystem continue to play a crucial role in the evolution of coherent optical technology. They are enabling higher-order modulation and many other advanced features that are helping optical engines like Infinera’s ICE6 to close in on Shannon’s limit for maximum theoretical spectral efficiency. They are also helping to enable the ultra-high baud rates that are contributing to significant reductions in the cost per bit, power consumption, and footprint of coherent optical transport.